1. Field of the Invention
The present invention relates to a method of programming a flash memory cell and, in particular, to a method of programming a flash memory cell which can reduce the size and implement a low power device.
2. Brief Description of the Prior Art
In general, the flash memory device such as a flash electrically erasable and programmable read only memory cell (EEPROM) has functions of electrically programming and erasing, and is classified into a stack-gate type and split-gate type depending on the shape of a constructed gate electrode.
Now, the structure and operation of conventional stack-gate type and split-gate type flash memory cells will be described below.
In the conventional stack-gate type flash memory cell, as shown in FIG. 1, a tunnel oxide film 4, floating gate 5, dielectric film 6 and control gate 7 are sequentially stacked on a silicon substrate 1, and a source and drain regions 2 and 3 are formed in the silicon substrate 1 on both sides of the floating gate 5, respectively. The operation of programming and erasing of the flash memory cell as described above is as follows.
To program an information to the flash memory cell, that is, to charge the floating gate 5 with an electric charge, +12 V is applied to the control gate 7, +5 V is applied to the drain region 3, and the ground voltage is applied to the source region 2 and silicon substrate 1 as shown in FIG. 2A . Then, a channel is formed in the silicon substrate 1 below the floating gate 5 due to the high voltage applied to the control gate 7, and the high electric field zone is formed in the silicon substrate 1 at the side of the drain region 3 due to the voltage applied to the drain region 3. At this time, a part of electrons existing in the channel receive the energy from the high electric field zone so as to be hot electrons, and a part of the hot electrons are injected to the floating gate 5 through the tunnel oxide film 4 by a vertical direction electrical field formed due to the high voltage applied to the control gate 7. Therefore, the threshold voltage (V.sub.T) of the flash memory cell rises due to the injection of the hot electron.
To erase the information programmed in the flash memory cell, that is, to discharge the electric charge stored in the floating gate 5, the ground voltage is applied to the control gate 7 and the silicon substrate 1, +12 V is applied to the source region 2, and the drain region 3 is floated as shown in FIG. 2B. Then, the electrons injected into the floating gate 5 are moved to the source region 2 due to the F-N (fowler-nordheim) tunneling phenomenon, whereby the threshold voltage V.sub.T of the memory cell is lowered.
The operation of erase of the flash memory cell is effectuated by the tunneling phenomenon which occurs locally between the source region 2 and the floating gate 5. Therefore, it is difficult to control the amount of electrons which moves to the source region 2 at the time of operation of erase, and a phenomenon that the floating gate 5 is not electrically recovered, that is, an over erasure occurs in case where the characteristics of the tunnel oxide film 4 is degraded. Such over erasure acts as a cause for degradation of the operational characteristics of the device.
On the other hand, in the split-gate type flash memory cell as shown in FIG. 3, a first insulating film 14, floating gate 15, second insulating film 16 and control gate 17 are sequentially stacked on a silicon substrate 11, and a third insulating film 18 and select gate 19 are stacked on the entire structure including such stack structure. A drain region 13 is formed in the silicon substrate 11 below one side of the floating gate 15, and a source region 12 is formed in the silicon substrate 11 spaced a predetermined distance from the floating gate 15.
The operation of programming and erasing the flash memory cell consisting of a gate electrode of such stack structure and a select transistor is as follows.
To program an information to the flash memory cell, that is, to charge the floating gate 15 with an electric charge, +12 V is applied to the control gate 17, +1.8 V is applied to the select gate 19, +5 V is applied to drain region 13, and the ground voltage is applied to the source region 12 and silicon substrate 11 as shown in FIG. 4A. Then, a select channel is formed in the silicon substrate 11 below the select gate 19 due to the voltage applied to the select gate 19, and a channel is formed in the silicon substrate 11 below the floating gate 15 due to the high voltage applied to the control gate 17. A drain current of 20 to 30 .mu.A flows through the select channel and at the same time a high electric field zone is formed in the channel below the floating gate 15. At this time, a part of electrons existing in the channel receive the energy from the high electric field zone so as to be hot electrons, and a part of the hot electrons are injected to the floating gate 15 through the first insulation film 14 by a vertical direction electric field formed due to the high voltage applied to the control gate 17. Therefore, the threshold voltage V.sub.T of the flash memory cell rises.
To erase the information programmed in the flash memory cell, that is, to discharge the electric charge stored in the floating gate 15, -12 V is applied to the control gate 17, +5 V is applied to the drain region 13, the ground voltage is applied to the select gate 19 and silicon substrate 11, and the source region 12 is floated, as shown in FIG. 4B. Then, the electrons injected into the floating gate 15 are moved to the source region 12 due to the F-N tunneling phenomenon, whereby the threshold voltage V.sub.T of the memory cell is lowered.
The read operation of the split-gate type flash memory cell is performed under the condition that the select transistor is turned-on. Therefore, it has an advantage in that the over-erasure phenomenon does not occur. However, since a leakage current can occur in case where the length of the select gate is reduced, it is difficult to reduce the size of memory cell.
In addition, the high voltage of 12 V or higher is applied to the control gate of the stack-gate type and split-gate type flash memory cell, and such high voltage is supplied from a charge pumping circuit which raises the power source voltage of about 5 V to the high voltage. Therefore, the flash memory device consisting of such memory cell has problems in that, first, a long hour is required for programming and the power consumption is large since a lot of time is required for the pumping operation which raises the power source voltage to the high voltage, and second, there is a difficulty in the manufacturing processes since the thickness of the second insulating film formed between the floating gate and the control gate must be more than two times thicker than that of the first insulating film to secure the reliability of the device.
Furthermore, recently, a low power memory device which uses the low voltage of 3.3 V or 2.5 V is required, and a method of reducing the voltage applied to the drain region at the time of programming is suggested as a method of implementing the low power memory deice. However, in case of using such method, the structure of the memory cell or drain junction must be changed to maintain the program characteristics to the same level as that of the conventional memory device using the power source voltage (for example, 5 V). Therefore, problems such as change in manufacturing processes and increase in process steps according to such change occurs.
In addition, as the other method of implementing the low power memory device, a method of adding a charge pumping circuit to the memory device to raise the voltage applied to the drain region at the time of programming to more than 5 V. However, this method also has a problem that the rise of drain potential by the charge pumping is impossible due to the drain current of 30 .mu.A or more occurring at the time of programming.